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EE 3402 Linear Integrated Circuits question paper, April/May 2023

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Question Paper Code : 30151

B.E./B.Tech. DEGREE EXAMINATIONS, APRIL/MAY 2023.

Fourth Semester

Electrical and Electronics Engineering

EE 3402 — LINEAR INTEGRATED CIRCUITS

(Common to : )

(Regulations 2021)

Time : Three hoursMaximum : 100 marks

Answer ALL questions.

PART A — (10 × 2 = 20 marks)

  1. 1.

    Mention the properties of silicon di-oxide.

  2. 2.

    What are the advantages of thin film resistor over diffused resistors?

  3. 3.

    Define Thermal drift.

  4. 4.

    Define Slew Rate.

  5. 5.

    What is a sample and hold circuit?

  6. 6.

    Define "Resolution" in ADC/DAC.

  7. 7.

    List out the applications of 555 timer in Astable mode.

  8. 8.

    Mention the types of phase detector in PLL.

  9. 9.

    List out the negative voltage regulator ICs.

  10. 10.

    Define "line regulation" in IC voltage regulator.

PART B — (5 × 13 = 65 marks)

  1. 11.
    (a)

    Explain the epitaxial growth, masking, etching and diffusion techniques in IC fabrication process with neat sketch.

  2. Or
  3. (b)

    Explain the different types of IC capacitor fabrication technique.

  4. 12.
    (a)

    With neat sketch explain the adder-subtractor combinational circuit with neat sketch.

  5. Or
  6. (b)

    Describe the working of differentiator and integrator. Draw the outputs for the inputs, sine and square waves.

  7. 13.
    (a)

    Explain the working of a second order active low pass filter with neat sketch and also draw its frequency response curve.

  8. Or
  9. (b)

    Explain the R-2R ladder and inverted R-2R ladder DACs.

  10. 14.
    (a)

    Briefly discuss the working of Phase Locked Loops(PLL).

  11. Or
  12. (b)

    With neat sketch, describe the working of a Astable multivibrator using 555 timer.

  13. 15.
    (a)

    Discuss the working of AD623 Instrumentation amplifier with neat sketch and also explain how it is used in the weight measurement.

  14. Or
  15. (b)

    Discuss the operation of Switched Mode Power Supply with neat sketch.

PART C — (1 × 15 = 15 marks)

  1. 16.
    (a)

    Design a circuit using Op-amp, which implements the following

    • (i)Vo = 5 +(10 sin wt) when Vi = 10 sin wt
    • (ii)Output is clipped above 5V when the input is 10 sin wt.
    • (iii)Output is clipped below 6V when the input is 15 sin wt.
    • (iv)Vo = 8V1 - 7V2
  2. Or
  3. (b)

    Find the gain of the programmable gains amplifier shown in the following figure when S1 alone is closed, S2 alone is closed, S3 alone is closed, S4 alone is closed and S1 and S3 is closed. [Figure: non-inverting op-amp with Vin at the + input and output Vout; a resistor chain of 2 kohm, 1 kohm, 500 ohm and 500 ohm in series from Vout to ground; the - input connects through switch S1 to Vout (top of the 2 kohm), through S2 to the 2 kohm/1 kohm junction, through S3 to the 1 kohm/500 ohm junction and through S4 to the 500 ohm/500 ohm junction]

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