Anna University · Regulation 2021
EC 3352 Digital Systems Design question papers
EC3352 Digital Systems Design previous year question papers from Anna University (Regulation 2021), with the full syllabus. Read online or download the PDF.
Third semester · Core · L T P C: 3 0 2 4
Question papers
- April/May 2025
Question paper code 90981
- November/December 2024
Question paper code 40979
- April/May 2024
Question paper code 50958
- November/December 2023
Question paper code 20925
- April/May 2023
Question paper code 30138
- November/December 2022
Question paper code 70085
Syllabus
Unit 1: Basic Concepts9 hours
Review of number systems · representation · conversions · Review of Boolean algebra · theorems · sum of product and product of sum simplification · canonical forms min term and max term · Simplification of Boolean expressions · Karnaugh map · completely and incompletely specified functions · Implementation of Boolean expressions using universal gates · Tabulation methods
Unit 2: Combinational Logic Circuits9 hours
Problem formulation and design of combinational circuits · Code-Converters · Half and Full Adders · Binary Parallel Adder · Carry look ahead Adder · BCD Adder · Magnitude Comparator · Decoder · Encoder · Priority Encoder · Mux/Demux · Case study: Digital trans-receiver / 8 bit Arithmetic and logic unit · Parity Generator/Checker · Seven Segment display decoder
Unit 3: Synchronous Sequential Circuits9 hours
Latches · Flip flops · SR · JK · T · D · Master/Slave FF · Triggering of FF · Analysis and design of clocked sequential circuits · Design · Moore/Mealy models · state minimization · state assignment · lock-out condition circuit implementation · Counters · Ripple Counters · Ring Counters · Shift registers · Universal Shift Register · Model Development: Designing of rolling display/real time clock
Unit 4: Asynchronous Sequential Circuits9 hours
Stable and Unstable states · output specifications · cycles and races · state reduction · race free assignments · Hazards · Essential Hazards · Fundamental and Pulse mode sequential circuits · Design of Hazard free circuits
Unit 5: Logic Families and Programmable Logic Devices9 hours
Logic families · Propagation Delay · Fan-In and Fan-Out · Noise Margin · RTL · TTL · ECL · CMOS · Comparison of Logic families · Implementation of combinational logic/sequential logic design using standard ICs · PROM · PLA and PAL · basic memory · static ROM · PROM · EPROM · EEPROM EAPROM