Skip to content
SmartFigureEdu

EC 3352 Digital Systems Design question paper, April/May 2025

Download PDFRepeated questions and unit-wise bank

Question Paper Code : 90981

B.E./B.Tech. DEGREE EXAMINATIONS, APRIL/MAY 2025.

Third Semester

Electronics and Communication Engineering

EC 3352 — DIGITAL SYSTEMS DESIGN

(Common to : Electronics and Telecommunication Engineering)

(Regulations 2021)

Time : Three hoursMaximum : 100 marks

Answer ALL questions.

PART A — (10 × 2 = 20 marks)

  1. 1.

    State De Morgan's law.

  2. 2.

    List the disadvantages of K-map.

  3. 3.

    Draw the logic diagram for full adder.

  4. 4.

    Distinguish between encoder and decoder.

  5. 5.

    Differentiate Moore and Mealy machine models.

  6. 6.

    What is the significance counters?

  7. 7.

    What do you mean by unstable state.

  8. 8.

    Define asynchronous sequential circuits?

  9. 9.

    What is the propagation delay of a circuit?

  10. 10.

    For the 4-input NAND gate, what is the fan-in of gate? If the NAND gate output is connected to two combinational function equation, then what is the fan-out of the NAND gate?

PART B — (5 × 13 = 65 marks)

  1. 11.
    (a)
    • (i)Convert the following Boolean function into Canonical and Standard SoP form. f = (p + q + r).(p + q + r').(p + q' + r).(p' + q + r).(6)
    • (ii)Simplify the function F(a, b, c, d) = Sum m(2, 3, 4, 8, 9, 10, 13, 14, 15) using K-map and implement the function using NAND gates only.(7)
  2. Or
  3. (b)

    Simplify using tabulation method for the function F(A, B, C, D) = Sum m(0, 1, 2, 4, 6, 8, 9, 11, 13, 15) and implement using NOR gates only.

  4. 12.
    (a)
    • (i)Design a binary to BCD converter and draw the logic diagram.(7)
    • (ii)Design a carry look ahead adder and explain the operation.(6)
  5. Or
  6. (b)
    • (i)Design a 2-bit magnitude comparator.(6)
    • (ii)Explain the operation of 4 : 2 encoder and 2 : 4 decoder with illustration.(7)
  7. 13.
    (a)
    • (i)Describe the operation of master/slave flip-flop.(6)
    • (ii)Analyze the given synchronous sequential circuit. [Figure: a T flip-flop with negative-edge clock; input a and Q feed an AND gate whose output is Z; a' (a through an inverter) and Q' feed a second AND gate; Z and the second AND gate output feed an OR gate whose output drives T.](7)
  8. Or
  9. (b)
    • (i)Design a 4-bit synchronous ring counter.(6)
    • (ii)Explain the operation of 4-bit universal shift register.(7)
  10. 14.
    (a)
    • (i)Show how state reduction is performed in asynchronous sequential circuits.(6)
    • (ii)Define race condition. Provide solution to overcome the race condition.(7)
  11. Or
  12. (b)

    What are hazards? What are the types of hazards? Design a hazard free circuits.

  13. 15.
    (a)

    Describe the TTL and CMOS logic families with necessary circuit diagram.

  14. Or
  15. (b)
    • (i)Elucidate the PLA architecture suitable for digital system design.(6)
    • (ii)Differentiate ROM and RAM? Explain the different types of ROM used in digital systems.(7)

PART C — (1 × 15 = 15 marks)

  1. 16.
    (a)
    • (i)Design the 8-bit arithmetic and logic unit.(7)
    • (ii)Realize the following expressions using PROM F1(a, b, c) = Sum m(0, 1, 2, 3, 5, 7), F2(a, b, c) = Sum m(1, 4, 5, 6).(8)
  2. Or
  3. (b)
    • (i)Implement the following Boolean functions using the PAL device for the following function: W(A, B, C, D) = Sum m(1, 12, 13); X(A, B, C, D) = Sum m(2, 7, 8, 11, 12, 13, 14, 15); Y(A, B, C, D) = Sum m(0, 2, 3, 4, 5, 8, 10, 12, 14); Z(A, B, C, D) = Sum m(2, 3, 4, 8, 12, 13)(7)
    • (ii)Design a rolling display using synchronous sequential circuits.(8)

Other EC3352 papers