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EC 3352 Digital Systems Design question paper, November/December 2023

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Question Paper Code : 20925

B.E./B.Tech. DEGREE EXAMINATIONS, NOVEMBER/DECEMBER 2023.

Third Semester

Electronics and Communication Engineering

EC 3352 — DIGITAL SYSTEMS DESIGN

(Common to : Electronics and Telecommunication Engineering)

(Regulations 2021)

Time : Three hoursMaximum : 100 marks

Answer ALL questions.

PART A — (10 × 2 = 20 marks)

  1. 1.

    Show the logic function of the Venn diagram shown in Fig. 1. [Fig. 1: Venn diagram of three overlapping circles x, y and z inside a rectangle.]

  2. 2.

    A burglar alarm for a bank is designed so that it senses four input signal lines. Line A is from the secret control switch, line B is from a pressure sensor under a steel safe in a locked closet, line C is from a battery-powered clock, and line D is connected to a switch on the locked closet door. The following conditions produce a logic 1 voltage on each line: (a) The control switch is closed. (b) The safe is in its normal position in the closet. (c) The clock is between 1000 and 1400 hours. (d) The closet door is closed. Write the equations of the control logic for the burglar alarm that produces a logic 1 (rings a bell) when the safe is moved and the control switch is closed, or when the closet is opened after banking hours or when the closet is opened with the control switch open.

  3. 3.

    Obtain the logic circuit diagram for a 4-line to 2-line priority encoder. Include an output V to indicate that at least one input is a 1.

  4. 4.

    Obtain the logic circuit diagram for a 4-bit odd parity checker.

  5. 5.

    A certain J-K flip-flop has tpd = 12 ns. What is the largest MOD counter that can be constructed from these flip-flops and still operate up to 10 MHz?

  6. 6.

    Design an n-bit Johnson counter.

  7. 7.

    List the general requirements for Essential hazard formation.

  8. 8.

    Differentiate critical and noncritical race.

  9. 9.

    Calculate noise margin low and noise margin high for the following voltage levels. VOH = 3.5V, VOL = 0.45 V, VIH = 2.35V, VIL = 0.66 V.

  10. 10.

    Write the working principle of EPROM.

PART B — (5 × 13 = 65 marks)

  1. 11.
    (a)

    Design a 4-bit Binary-Coded Decimal (BCD) input/single output logic circuit that will be used to distinguish digits that are greater than or equal to 5 from those that are less than 5. The input will be the BCD representation of the decimal digits 0,1...9, and the output should be 1 if the input is 5, 6, 7, 8, or 9 and 0 if the input is less than 5. Obtain the following.

    • (i)Minimum SOP form
    • (ii)Minimum POS form.
  2. Or
  3. (b)

    Use the tabular procedure to simplify the give expression F(V, W, X, Y, Z) = m(0, 4, 12, 16, 19, 24, 27, 28, 29, 31) in SOP form and draw the circuit using only NAND gates.

  4. 12.
    (a)

    Design a 4-bit adder that should have a computational complexity of O(1).

  5. Or
  6. (b)

    Design a logic circuit that compares two 4-bit inputs A and B and produces their relative magnitudes.

  7. 13.
    (a)

    Deduce a logic circuit diagram to produce the following sequences of input and output signals. [Clock cycle: t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10; w: 0 1 0 1 1 0 1 1 1 0 1; z: 0 0 0 0 1 0 0 1 1 0 0]

  8. Or
  9. (b)

    A universal shift register can shift in both the left-to-right and right-to-left directions, and it has parallel-load capability. Draw a circuit for such a shift register.

  10. 14.
    (a)

    What is a flow table? Derive a logic circuit diagram for the flow table given below. [Flow table, columns x1x2 = 00, 01, 11, 10 (next state, output; circled = stable). Row a: (a),0 | (a),0 | (a),0 | b,0. Row b: a,0 | a,0 | (b),1 | (b),0.]

  11. Or
  12. (b)

    Using tabular method, reduce the number of states in the state table given below. [State table: present state q; next state q* for xy = 00, 01, 10, 11; output Z. A: B, A, F, D; 1. B: E, A, D, C; 1. C: A, F, D, C; 0. D: A, A, B, C; 1. E: B, A, C, B; 1. F: A, F, B, C; 0.]

  13. 15.
    (a)

    Discuss about the various programmable logic devices and implement the following functions using PLA. F1 = (AB + AC + BC)'; F2 = AB + AC + A'B'C'

  14. Or
  15. (b)

    Compare and contrast the features of TTL and CMOS logic styles and implement XOR and XNOR gates using CMOS logic style.

PART C — (1 × 15 = 15 marks)

  1. 16.
    (a)

    Design a digital combinational lock using pulse mode sequential circuit that takes two inputs X and Y and produces two outputs Lock and Open. The input pulse sequence required to open the lock is X-X-Y-X-Y. Implement the next state and output forming logic using a ROM.

  2. Or
  3. (b)

    Design a 4-bit ALU to perform the following arithmetic and logic operations. - Transfer A - Increment A - Addition - Addition with carry - Subtract with borrow - Subtraction - Decrement A - Transfer A - OR - XOR - AND - Complement A.

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