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EC 3352 Digital Systems Design question paper, April/May 2024

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Question Paper Code : 50958

B.E./B.Tech. DEGREE EXAMINATIONS, APRIL/MAY 2024.

Third Semester

Electronics and Communication Engineering

EC 3352 — DIGITAL SYSTEMS DESIGN

(Common to : Electronics and Telecommunication Engineering)

(Regulations 2021)

Time : Three hoursMaximum : 100 marks

Answer ALL questions.

PART A — (10 × 2 = 20 marks)

  1. 1.

    A and B are integer variables in a computer program, with A = (25)10 and B = -(46)10. Assuming that the computer uses 8-bit two's complement arithmetic, show how it would compute A - B, B - A and -A - B.

  2. 2.

    Draw the logic diagram using only two input NAND gates to implement the following expression F = (AB + A'B') (CD' + C'D).

  3. 3.

    A network router connects multiple computers together and allows them to send messages to each other. If two or more computers send message simultaneously, they collide and the messages must be resent. Implement a collision detection circuit using discrete ICs for a router that connects 3 computers.

  4. 4.

    Obtain the logic circuit diagram for a one bit magnitude comparator.

  5. 5.

    Design a 4-bit serial adder.

  6. 6.

    Draw the state diagram for moore model based sequence detector to detect the sequence 101 with one bit overlap.

  7. 7.

    Distinguish stable and unstable states.

  8. 8.

    What is pulse mode sequential circuit?

  9. 9.

    Construct an open-collector TTL 3-input NAND gate.

  10. 10.

    Show the memory cycle timing waveform for the memory read operation.

PART B — (5 × 13 = 65 marks)

  1. 11.
    (a)

    Develop a minimized Boolean implementation of a "ones count" circuit that works as follows. The subsystem has four inputs A, B, C, D and generates a 3-bit output : XYZ . XYZ is 000 if none of the inputs are 1, 001 if one input is 1,010 if two inputs are 1, 011 if three inputs are 1 and 100 if all four inputs are 1.

  2. Or
  3. (b)

    Using Karnaugh map method, simplify the following Boolean function. F(A, B, C, D) = Sum m(4, 6, 7, 13, 14) + d(5, 10, 12, 15)

  4. 12.
    (a)

    Design a 4-bit adder that should have a computational complexity of O(1).

  5. Or
  6. (b)

    Develop the truth table and deduce a logic circuit for the BCD to seven segment display decoder using common anode LEDs.

  7. 13.
    (a)

    Design a synchronous counter that counts as 000, 010, 101, 110, 000, 101, ... Ensure that unused states of 001, 011, 100 and 111 go to 000 on next clock pulse. Use J-K flip-flops. How will the counter hardware look like if the unused states are to be considered as "don't cares"?

  8. Or
  9. (b)

    Design a pulse train generator using a shift register to generate the following sequence 10111101011110....

  10. 14.
    (a)

    An asynchronous sequential circuit has two internal states and one output. The excitation and output functions describing the circuit are as follows: Y1 = x1x2 + x1y2' + x2'y1; Y2 = x2 + x1y1'y2 + x1'y1; z = x2 + y1

    • (i)Draw the logic diagram of the circuit.(3)
    • (ii)Derive the transition table and output map.(5)
    • (iii)Obtain a flow table for the circuit.(5)
  11. Or
  12. (b)

    For the reduced flow table shown in Fig. 1 obtain a binary state assignment without critical race conditions. Also obtain the logic diagram of the circuit using NAND latches and gates. [Fig. 1: reduced flow table, columns x1x2 = 00, 01, 11, 10 (entries are next state, output; circled = stable). Row a: (a),0 | (a),1 | b,- | d,-. Row b: a,- | (b),0 | (b),0 | c,-. Row c: a,- | -,- | d,- | (c),0. Row d: a,- | a,- | (d),1 | (d),1.]

  13. 15.
    (a)

    The following are the specifications of the Schottky TTL 74LS00 quadruple 2-input NAND gates. Calculate the fan-out, power dissipation, propagation delay and noise margin of the Schottky NAND gate. [Table: Parameter, Name, Value. VCC, Supply voltage, 5V; ICCH, High-level supply current (four gates), 10mA; ICCL, Low-level supply current (four gates), 20mA; VOH, High-level output voltage (min), 2.7V; VOL, Low-level output voltage (max), 0.5V; VIH, High-level input voltage(min), 2V; VIL, Low-level input voltage(max), 0.8V; IOH, High-level output current(max), 1mA; IOL, Low-level output current(max), 20mA; IIH, High-level input current(max), 0.05mA; IIL, Low-level input current(max), 2mA; tPLH, Low-to-High delay, 3 ns; tPHL, High-to-low delay, 3 ns.]

  14. Or
  15. (b)

    Obtain a BCD to excess-3 code converter using PLA program table.

PART C — (1 × 15 = 15 marks)

  1. 16.
    (a)

    Deduce the logic diagram for the state diagram shown in Fig. 2 using one hot encoding method. Compare the hardware implementation resources with binary encoding method. [Fig. 2: four-state diagram. Reset leads to state 1 (Bulb off), which stays on "Button not pushed" and goes to state 2 on "Button pushed"; state 2 (Bulb on) stays on "Button pushed" and goes to state 3 on "Button not pushed"; state 3 (Bulb on) stays on "Button not pushed" and goes to state 4 on "Button pushed"; state 4 (Bulb off) stays on "Button pushed" and goes to state 1 on "Button not pushed".]

  2. Or
  3. (b)

    Design a circuit that controls the elevator door in a three story building as given in Fig. 3. Let M is a logic signal that indicates the elevator is moving (M = 1) or stopped (M = 0). F1, F2 and F3 are floor indicator signals that are normally LOW, and they go HIGH only when the elevator is positioned at that particular floor. For example, when the elevator is lined with second floor where M = 0, F2 = 1 and F1 = F3 = 0. The circuit output is OPEN which is identified as "Low" when moving and will go "HIGH" when the elevator door is to be opened at the particular floor. Since the elevator cannot be lined up with more than one floor at a time, only one of the floor inputs can be HIGH at any given time. This means that all those cases in the truth table where more than one floor input is a 1 are assumed to be don't care conditions. Obtain the simplified expression using K-Map and draw the logic diagram for the expression. [Fig. 3: block "Elevator circuit" with inputs M, F1, F2, F3 and output OPEN.]

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