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EC 3352 Digital Systems Design question paper, April/May 2023

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Question Paper Code : 30138

B.E./B.Tech. DEGREE EXAMINATIONS, APRIL/MAY 2023.

Third Semester

Electronics and Communication Engineering

EC 3352 — DIGITAL SYSTEMS DESIGN

(Common to : Electronics and Telecommunication Engineering)

(Regulations 2021)

Time : Three hoursMaximum : 100 marks

Answer ALL questions.

PART A — (10 × 2 = 20 marks)

  1. 1.

    Convert the decimal number 431 to binary.

  2. 2.

    State DeMorgan's theorem.

  3. 3.

    What is an encoder?

  4. 4.

    State the difference between parity generator and parity checker.

  5. 5.

    How are the outputs of Mealy model and Moore model decided?

  6. 6.

    What is a universal shift register?

  7. 7.

    When does a race condition exist in an asynchronous sequential circuit?

  8. 8.

    What is the cause of an essential hazard?

  9. 9.

    Define noise margin.

  10. 10.

    List the types of ROMs with their expansion.

PART B — (5 × 13 = 65 marks)

  1. 11.
    (a)
    • (i)Simplify the Boolean function (BC' + A'D)(AB' + CD') to a minimum number of literals.(6)
    • (ii)Express the following function as a sum of minterms and as a product of maxterms: F(A, B, C, D) = B'D + A'D + BD (4 + 3)(7)
  2. Or
  3. (b)

    Simplify the following function using Karnaugh map and implement it with two level NOR gate circuits. F = wx' + y'z' + w'yz'.

  4. 12.
    (a)

    Implement a full adder with two half adders and an OR gate by deriving Boolean expression from its truth table and draw the logic circuit.

  5. Or
  6. (b)

    Implement the following function with a multiplexer. F(A, B, C, D) = Sum(0, 2, 5, 8, 10, 14)

  7. 13.
    (a)

    Explain the principle of JK flip flop with logic diagram, graphic symbol, characteristic table, and characteristic equation.

  8. Or
  9. (b)

    Describe the principle of BCD ripple counter with state diagram and logic diagram.

  10. 14.
    (a)

    Find a critical race-free state assignment for the reduced flow table shown in Figure Q 14 (a). [Figure 14 (a): reduced flow table, columns 00, 01, 11, 10 (circled = stable). Row a: (a), d, (a), c. Row b: a, (b), (b), d. Row c: d, (c), b, (c). Row d: (d), (d), (e), (d). Row e: f, c, (e), c. Row f: (f), b, a, (f).]

  11. Or
  12. (b)

    Describe various types of hazards and the methods to eliminate hazards in combinational and sequential circuits.

  13. 15.
    (a)
    • (i)Draw and explain CMOS logic circuits.(7)
    • (ii)Explain a TTL gate with totem pole output.(6)
  14. Or
  15. (b)
    • (i)Using 64 x 8 ROM chips with an enable input, construct a 512 x 8 ROM with 8 chips and a decoder.(7)
    • (ii)Draw a PLA circuit to implement the functions F1 = A'B + AC + A'BC'; F2 = (AC + AB + BC)'(6)

PART C — (1 × 15 = 15 marks)

  1. 16.
    (a)

    Simplify the following Boolean function by using the tabulation method. F = Sum(0, 1, 2, 8, 10, 11, 14, 15)

  2. Or
  3. (b)

    A sequential circuit has two JK flip flops A and B and one input X. The circuit is described by the following flip flop input equations. JA = x, KA = B; JB = x, KB = A'

    • (i)Derive the state equations A (t + 1) and B (t + 1) by substituting the input equations for the J and K variables.(8)
    • (ii)Draw the state diagram of the circuit.(7)

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