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EC 3353 Electronic Devices and Circuits question paper, April/May 2024

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Question Paper Code : 50959

B.E./B.Tech. DEGREE EXAMINATIONS, APRIL/MAY 2024.

Third Semester

Electronics and Communication Engineering

EC 3353 — ELECTRONIC DEVICES AND CIRCUITS

(Common to : Electronics and Telecommunication Engineering)

(Regulations 2021)

Time : Three hoursMaximum : 100 marks

Answer ALL questions.

PART A — (10 × 2 = 20 marks)

  1. 1.

    Determine the diode current at 20°C for a Silicon diode with reverse saturation current of 50 nA and an applied forward bias of 0.6 V.

  2. 2.

    Compare half wave and full wave rectifier.

  3. 3.

    What is an Operating point in BJT?

  4. 4.

    What is the need for biasing?

  5. 5.

    State the importance of coupling capacitor in an amplifier.

  6. 6.

    Define CMRR.

  7. 7.

    List the advantages of negative feedback.

  8. 8.

    What are the necessary conditions for oscillation?

  9. 9.

    Why is heat sink required in power amplifiers?

  10. 10.

    What is the angle of conduction of class B and Class AB power amplifiers?

PART B — (5 × 13 = 65 marks)

  1. 11.
    (a)

    Derive the average voltage and RMS voltage of a full wave rectifier output. Also compute the average voltage and RMS voltage when the peak input voltage is 20 V.

  2. Or
  3. (b)

    For the circuit shown in Figure below find (i) the output voltage across 10 kohm (ii) the voltage drop across series resistance 5 kohm (iii) the current through Zener diode (iv) the current through 10 kohm. [Figure: 120 V source with series resistor R = 5 kohm (current I) feeding a 50 V Zener diode (current IZ) in parallel with a 10 kohm load (current IL).]

  4. 12.
    (a)

    For the voltage divider bias circuit for biasing BJT, derive the expression for ICQ and VCEQ.

  5. Or
  6. (b)

    [Figure: n-channel MOSFET amplifier, +18 V supply; gate divider 91 Mohm (to +18 V) and 15 Mohm (to ground); input Vi coupled to the gate through a capacitor; drain to +18 V through 6.8 kohm, output Vo through a coupling capacitor; source to ground through 3.3 kohm with a bypass capacitor; yos = 35 micro S, yfs = 6000 micro S.] Find the output voltage Vo, for the input voltage Vin = 4 mV.

  7. 13.
    (a)

    Analyze and determine the gain of differential amplifier using BJT in common mode and difference mode.

  8. Or
  9. (b)

    Explain the effects on cut off frequencies and bandwidth of multistage amplifier MOSFET frequency response.

  10. 14.
    (a)

    Derive the voltage gain, input impedance and output impedance of the following voltage series feedback amplifier configuration. [Figure: block diagram: source Vs in series with feedback voltage Vf drives the input Vi of an "Amplifier with gain A"; output Vo across RL is sampled in parallel by a "Feedback Circuit beta" giving Vf = beta Vo in series with the input.]

  11. Or
  12. (b)

    Explain the working phase shift oscillator and determine the oscillating frequency.

  13. 15.
    (a)

    Explain the working of Buck type DC/DC convertor with relevant circuit diagrams

  14. Or
  15. (b)

    Describe the working of class A and Class B amplifier using BJT.

PART C — (1 × 15 = 15 marks)

  1. 16.
    (a)

    Design an electronic circuit which requires a constant DC voltage of 8V for its operation. The available supply is 12V ± 1V. The electronic device can be assumed to be purely resistive of resistance 2 kohm. Design a simple shunt regulator using Zener diode. Choose appropriate resistance values for the design.

  2. Or
  3. (b)

    Calculate the oscillator frequency for an FET Hartley oscillator as in Figure for the following circuit values: C = 250 pF, L1 = 1.5 mH, L2 = 1.5 mH, and M = 0.5 mH. [Figure: FET Hartley oscillator: drain fed from +VDD through RFC and coupled through Cc to the tank; gate coupled through CG with RG to ground; tank of L1 and L2 (mutual inductance M, junction grounded at the source) with C across them.]

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