Anna University · Regulation 2021
EC 3552 VLSI and Chip Design question papers
EC3552 VLSI and Chip Design previous year question papers from Anna University (Regulation 2021), with the full syllabus. Read online or download the PDF.
Fifth semester · Core · L T P C: 3 0 0 3
Question papers
- April/May 2025
Question paper code 90991
- November/December 2024
Question paper code 40989
- April/May 2024
Question paper code 50968
- November/December 2023
Question paper code 20935
Syllabus
Unit 1: MOS Transistor Principles9 hours
MOS logic families (NMOS and CMOS) · Ideal and Non Ideal IV Characteristics · CMOS devices · MOS(FET) Transistor Characteristic under Static and Dynamic Conditions · Technology Scaling · power consumption
Unit 2: Combinational Logic Circuits9 hours
Propagation Delays · stick diagram · Layout diagrams · Examples of combinational logic design · Elmore's constant · Static Logic Gates · Dynamic Logic Gates · Pass Transistor Logic · Power Dissipation · Low Power Design principles
Unit 3: Sequential Logic Circuits and Clocking Strategies9 hours
Static Latches and Registers · Dynamic Latches and Registers · Pipelines · Nonbistable Sequential Circuits · Timing classification of Digital Systems · Synchronous Design · Self-Timed Circuit Design
Unit 4: Interconnect, Memory Architecture and Arithmetic Circuits9 hours
Interconnect Parameters · Capacitance · Resistance · and Inductance · Electrical Wire Models · Sequential digital circuits: adders · multipliers · comparators · shift registers · Logic Implementation using Programmable Devices (ROM, PLA, FPGA) · Memory Architecture and Building Blocks · Memory Core and Memory Peripherals Circuitry
Unit 5: ASIC Design and Testing9 hours
Introduction to wafer to chip fabrication process flow · Microchip design process & issues in test and verification of complex chips · embedded cores and SOCs · Fault models · Test coding · ASIC Design Flow · Introduction to ASICs · Introduction to test benches · Writing test benches in Verilog HDL · Automatic test pattern generation · Design for testability · Scan design: Test interface and boundary scan